1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to a semiconductor memory device equipped with an isolation signal generating circuit for controlling electrical isolation between a cell array and a sense amplifier. The present invention is also concerned with a semiconductor memory device of a hierarchical arrangement of word drivers for driving word lines.
2. Description of the Related Art
First, a first conventional semiconductor memory device will be described with reference to FIGS. 1 and 2.
FIG. 1 is a circuit diagram of a part of a DRAM (Dynamic Random Access Memory), which is the first conventional semiconductor memory device. The DRAM shown in FIG. 1 employs a shared sense amplifier formation in which a sense amplifier is shared by neighboring cell arrays. The DRAM also employs a hierarchical arrangement of word drivers so that each word driver includes a main word driver and a sub word driver.
The DRAM includes cell arrays 1-9, main word drivers 10-12, and sub word drivers 13-24. The main word drivers 10-12 drive main word lines. The sub word drivers receive output signals of the main word drivers 10-12 and sub word selection signals that are output by a sub word selection signal generating circuit (not illustrated for the sake of simplicity), and select involved memory cells.
Column decoders 25-27 decode a column address signal and select columns based on decoding. Sense amplifier parts 28-39 are shared by neighboring cell arrays in a wiring direction of bit lines, and include a sense amplifier and a bit line precharge circuit.
The DRAM includes row block selecting signal lines 40-45, and a timing signal line 46. The DRAM includes isolation signal generating circuits 47-52, which receive the row block selecting signals and a timing signal, and thus generate isolation signals for controlling electrical connection/disconnection between the neighboring cell arrays and the sense amplifier parts in the direction in which the bit lines run.
The DRAM includes isolation signal lines 53-58, and isolation circuits 59-76. The isolation signal lines 53-58 carry isolation signals respectively output by the isolation signal generating circuits 47-52. The isolation circuits 59-76 respectively have, as switching elements, isolation transistors, which are turned ON/OFF by the isolation signals in order to control electrical connection and disconnection between the cell arrays and sense amplifiers which are adjacent in the direction in which the bit lines run.
In the DRAM thus configured, a read/write operation enables the cell arrays connected to selected main word lines, sub word drivers and sense amplifier parts associated with the selected main word lines. Further, the isolation transistors of the isolation circuits involved in the above read/write operation.
FIG. 2 is a circuit diagram illustrating an isolation operation performed in the DRAM that is described as the first conventional semiconductor memory device in the present specification. For example, when the word lines driven by the main word driver 11 are selected, the cell arrays 4-6, the sub word drivers 17-20, and the sense amplifier parts 31-36 are enabled within the circuit part shown in FIG. 2, while the isolation transistors of the isolation circuits 62-64 and 71-73 are turned OFF. The isolation transistors of the isolation circuits 59-61, 65-70, and 74-76 are maintained in the ON state.
Thus, electrical connections are made between the cell array 4 and the sense amplifier parts 31 and 34, between the cell array 5 and the sense amplifier parts 32 and 35, and between the cell array 6 and the sense amplifier parts 33 and 36. In contrast, the cell arrays 1, 2, 3, 7, 8 and 9 are respectively disconnected from the sense amplifier parts 31, 32, 33, 34, 35 and 36.
A description will be given, with reference to FIGS. 3 through 5, of a second conventional DRAM, which employs the shared amplifier formation. The DRAM also employs a hierarchical arrangement of word drivers so that each word driver includes a main word driver and a sub word driver. Further, each isolation signal generating circuit is hierarchically arranged so as to include a main isolation signal generating circuit and a sub isolation signal generating circuit.
Referring to FIG. 3, the second conventional DRAM includes row block selection signal lines 77-82, a timing signal line 83, main isolation signal generating circuits 84-89, and main isolation signal lines 90-95. The main isolation signal generating circuits 84-89 receive the row block selection signal lines 77-82 and a timing signal carried over the timing signal line 83, and generate resultant main isolation signals, which are transferred over the main isolation signal lines 90-95.
The second conventional DRAM includes column block selection signal lines 96-101, sub isolation signal generating circuits 102-137, and sub isolation signal lines 138-155. The sub isolation signal generating circuits 102-137 receive the main isolation signals and column block selection signals carried over the column block selection signal lines 96-101, and generate resultant sub isolation signals, which are transferred over the sub isolation signal lines 138-155.
The second conventional DRAM includes sub word drivers 156-173, and has the same cell arrays 1-9, main word drivers 10-12, column decoders 25-27, the sense amplifier parts 28-39, and isolation circuits 59-76 as those of the first conventional DRAM.
In the second conventional DRAM, a read/write operation enables the cell arrays connected to selected main word lines, sub word drivers and sense amplifier parts associated with the selected main word lines. Further, the isolation transistors of the isolation circuits involved in the above read/write operation.
FIG. 4 is a circuit diagram illustrating an isolation operation performed in the second conventional. For example, when memory cells in the cell array 5 are selected, the cell array 5, the sub word drivers 164 and 165, the sub isolation signal generating circuits 110, 111, 128 and 129, and the sense amplifier parts 32 and 35 are enabled within the circuit part shown in FIG. 4.
Thus, the isolation transistors of the isolation circuits 63 and 72 are turned OFF, while those of the isolation circuits 59-62, 64-71, and 73-76 are maintained in the ON state. Thus, connections of the cell array 5 with the sense amplifier parts 32 and 35 are made, while the cell arrays 2 and 8 are disconnected from the sense amplifier parts 32 and 35, respectively.
FIG. 5 is a circuit diagram of a configuration of the main isolation signal generating circuits and the sub isolation signal generating circuits employed in the second conventional DRAM. A main isolation signal generating circuit 174 includes a NAND circuit 175, an inverter 176, PMOS (P-channel Metal Oxide Semiconductor) transistors 177-179, and NMOS (N-channel MOS) transistors 180-182.
A sub isolation signal generating circuit 183 includes PMOS transistors 184-187, and NMOS transistors 188-191. A symbol VPP denotes a boosted voltage obtained by boosting a power supply voltage supplied from the outside of the DRAM. A symbol VSS denotes a ground potential.
A description will be given, with reference to FIGS. 6 through 8, of a third conventional DRAM.
FIG. 6 illustrates a layout of a core part of the third conventional DRAM, which employs the shared sense amplifier formation and the hierarchical arrangements of the word drivers and isolation signal generating circuits. Further, the third conventional DRAM includes a hierarchical arrangement of sub word selection signal generating circuits (1/4 signal generating circuits) so that each of the circuits is made up of a main sub-word selection signal generating circuit (main 1/4 signal generating circuit) and a sub sub-word selection signal generating circuit (sub 1/4 signal generating circuit).
The layout shown in FIG. 6 includes a core part 192, cell areas 193-196, main word driver areas 197 and 198, sub word driver areas 199-204, sense amplifier areas 205-210, MS cross areas 211-213, and SS cross areas 215-223. The cell areas 193-196 include cell arrays. The main word driver areas 197 and 198 include main word drivers. The sub word driver areas 199-204 include sub word drivers. The sense amplifier areas 205-210 include sense amplifiers. The MS cross areas 211-213 include main sub-word selection signal generating circuits and main isolation signal generating circuits. The SS cross areas 215-223 include sub sub-word selection signal generating circuits, sub isolation signal generating circuits, and bit line precharge signal generating circuits.
FIG. 7 is a circuit diagram of a part of the core part of the third conventional DRAM. There are illustrated address signal lines 224, main word drivers 225-227, sub word drivers 228-247, main sub-word selection signal generating circuits 248-251, sub sub-word selection signal generating circuits 252-259, main isolation signal generating circuits 260 and 261, sub isolation signal generating circuits 262-265, and bit line precharge signal generating circuits 266 and 267.
Arrows of broken lines denote signal lines that carry a signal. This signal has an amplitude having the maximum level (corresponding to a power supply potential on the high-potential side) corresponding to a step-down voltage VII obtained by internally stepping down the power supply voltage VDD supplied from the outside of the DRAM, and the minimum level (corresponding to a power supply potential on the low-potential side) corresponding to the ground potential VSS. Arrows of solid lines denote signal lines that carry the following signal. This signal has an amplitude having the maximum level (corresponding to a power supply potential on the high-potential side) corresponding to the boosted voltage VPP, and the minimum level (low-potential) corresponding to the ground level VSS.
More particularly, the address signal lines 224 described by broken-line arrows carry the step-down potential VII that is the power supply potential on the high-potential side and is obtained by stepping down the external power supply voltage VDD. The following signal lines by solid-line arrows carry the boosted potential VPP that is the power supply potential on the low-potential side: the main word lines extending from the main word drivers 225-227, the main sub-word selection signal lines extending from the main sub-word selection signal generating circuits 248-251, the main isolation signal lines extending from the main isolation signal generating circuits 260 and 261, the sub isolation signal lines extending from the sub isolation signal generating circuits 262-265, and bit line precharge signal lines extending from the bit line precharge signal generating circuits 266 and 267.
FIG. 8 is a circuit diagram of a circuit configuration arranged in the SS cross area in the core part of the third conventional DRAM. Referring to FIG. 8, there are illustrated sub isolation signal generating circuits 268 and 269, each of which circuit includes PMOS transistors 270 and 271, NMOS transistors 272 and 273, and inverters 274 and 275. There are also illustrated a bit line precharge signal generating circuit 276 composed of a NOR circuit 277 and an inverter 278. A sub sub-word selection signal generating circuit 279 is made up of a PMOS transistor 280, NMOS transistors 281 and 282, and inverters 283-285. A sub word driver 286 is made up of PMOS transistor 287 and NMOS transistors 288 and 289.
However, the second conventional DRAM shown in FIG. 3 has a disadvantage in that the boosted potential VPP is used as the power supply potential of the main isolation signals on the high-potential side and the sub isolation signals. This consumes an increased amount of power.
The third conventional DRAM shown in FIG. 7 (FIG. 6) has a disadvantage in that the potential VPP is used as the power supply potential of the main sub-word selection signals on the high-potential side and sub sub-word selection signals. This increases power consumption.
It is a general object of the present invention to provide a semiconductor memory device in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a semiconductor memory device equipped with a hierarchical arrangement of isolation circuits controlling electrical isolation between cell arrays and sense amplifiers, wherein reduced power can be consumed.
Another object of the present invention is to provide a semiconductor memory device equipped with a hierarchical arrangement of sub word selection signal generating circuits, wherein reduced power can be consumed.
The above objects of the present invention are achieved by a semiconductor memory device comprising: isolation circuits disconnecting cell arrays from sense amplifiers; and isolation signal generating circuits generating isolation signals that control the isolation circuits, the isolation signal generating circuits being hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits, the sub isolation signal generating circuits generating sub isolation signals having a first potential on a high-potential side, the main isolation signal generating circuits generating main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.
According to the above semiconductor memory device, the potential of only the sub isolation signals on the high-potential side is the first potential, while the potential of the main isolation signals on the high potential side is the second potential lower than the first potential. It is therefore possible to reduce the number of signal lines via which the first potential serving as a high-potential side power supply potential is supplied.
The above objects of the present invention are also achieved by a semiconductor memory device comprising: main word drivers that drive word lines and are hierarchically divided into main word drivers and sub word drivers; and sub word selection signal generating circuits that select sub word lines and are hierarchically divided into main sub-word selection signal generating circuits and sub sub-word selection signal generating circuits, the sub sub-word selection signal generating circuits generating sub sub-word selection signals having a first potential on a high-potential side, the main sub-word selection signal generating circuits generating main sub-word selection signals having a second potential on the high-potential side, the second potential being lower than the first potential.
According to the above semiconductor memory device, the potential of only the sub sub-word selection signals on the high-potential side is the first potential, while the potential of the main sub-word selection signals on the high-potential side is the second potential lower than the first potential. It is therefore possible to reduce the number of signal lines via which the first potential serving as a high-potential side power supply potential is supplied.
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings, in which:
FIG. 1 is a circuit diagram of a part of a first conventional DRAM;
FIG. 2 is a circuit diagram for explaining an isolating operation of the first conventional DRAM;
FIG. 3 is a circuit diagram of a second conventional DRAM;
FIG. 4 is a circuit diagram for explaining an isolating operation of the second conventional DRAM;
FIG. 5 is a circuit diagram of a main isolation signal generating circuit and a sub isolation signal generating circuit, both being provided in the second conventional DRAM;
FIG. 6 is a diagram of a layout of a core part of a third conventional DRAM;
FIG. 7 is a circuit diagram of a part of the core part of the third conventional DRAM;
FIG. 8 is a circuit diagram of a circuit configuration arranged in an SS cross area of the core part of the third conventional DRAM;
FIG. 9 is a circuit diagram of a first embodiment of the present invention;
FIG. 10 is a circuit diagram of a circuit configuration of a main isolation signal generating circuit and a sub isolation signal generating circuit, both being provided in the first embodiment of the present invention;
FIG. 11 is a circuit diagram of another circuit configuration of the sub isolation signal generating circuit employed in the first embodiment of the present invention;
FIG. 12 is a circuit diagram of a part of a core part of a second embodiment of the present invention; and
FIG. 13 is a circuit diagram of a circuit configuration arranged in an SS cross area of the core part of the second embodiment of the present invention.